A research team has designed a low-area, low-power reversible full adder based on a two-transistor multiplexer, aimed at image addition operations in hardware. The circuit addresses one of the classic bottlenecks of reversible computing: the unavoidable tension between reversible logic, which in principle dissipates no energy when erasing information, and the real cost in transistor count, silicon area and delay that proposed implementations have typically carried so far.

The motivation behind the work is image addition, an elementary but intensive operation in artificial vision processors and embedded systems with a tight energy budget. In that context, every milliwatt and every square micrometre counts, making an adder architecture that combines reversibility with a minimal footprint attractive for future low-power accelerators.

The core element of the design is a multiplexer built from just two transistors, acting as the basic block to generate the logical functions required by the full adder without resorting to heavier conventional structures. This simplification reduces the overall component count and, with it, the occupied area and dissipated power, while preserving the reversibility of the circuit, that is, the ability to reconstruct the inputs from the outputs without loss of information.

The significance of the result is twofold. On the one hand, it provides a reusable building block for reversible circuit designers seeking efficiency without giving up on theory. On the other, it opens the door to concrete applications in embedded image processing, where the addition of pixel matrices is one of the dominant operations. The work fits into the research line exploring how to bring the theoretical advantages of reversible computing into practical implementations on conventional CMOS technologies.