A team has demonstrated logical error suppression in a rotated surface-code memory implemented on a cloud-accessible IBM Nighthawk r2 superconducting processor. Quantum error correction can reduce the logical error rate exponentially with code distance when physical noise is below threshold, but turning that promise into hardware requires coordinating gates, mid-circuit measurements and qubit coherence in the face of device variation, asymmetric noise and spatiotemporal correlations.

The authors optimized the syndrome extraction circuit by combining short readout, fused measurement and reset, and an XX echo on data qubits during ancilla readout. Compared with standard readout without reset or echo, the recipe cuts the median per-round logical error rate by a factor of 3.8 in the X basis and 1.4 in the Z basis. Performance also varies across the tested qubit placements on the processor, which they attribute to differences in qubit quality.

In memory experiments of up to 150 rounds, the advantage associated with code distance weakens and long-lived correlations appear that may reflect a persistent error component. Under the applied optimization, increasing the protected distance from 3 to 6 — while holding the other fixed — lowers the per-round logical error rate from 0.53 % to 0.24 % in Z memory and from 0.52 % to 0.22 % in X memory, with maximum-likelihood-decoding error-suppression factors of 1.68 and 1.85, respectively.

The results link circuit compilation and optimization to surface-code memory performance — and its limitations — and point toward quantum-processor and error-correction-circuit codesign as a route to fault-tolerant quantum computing primitives on current cloud-accessible quantum hardware.