A team presents NeST (Nested Shuttling Tracks), the first co-design of a quantum code and silicon spin-qubit hardware aimed at low-density parity-check (qLDPC) codes. These codes reach encoding rates of up to 50% at useful distances, but their checks are long-range group actions rather than local neighbourhoods. Until now that connectivity was supplied by neutral atoms; NeST achieves it through coherent transport of qubit blocks via electron shuttling, on microsecond rather than millisecond timescales.

The architecture mimics the geometry of a family of non-abelian groups through a hierarchy of nested conveyor-belt loops on a square lattice of shuttling tracks. Every group multiplication becomes a rigid, globally controlled motion of whole qubit trains, circumventing the limitation that spin qubits travel along fabricated tracks rather than free space. A code search over this family returns rate-20% mitten codes up to [[1400,280,≤28]], with circuit-level simulations that, including shuttling dephasing, yield thresholds above 10⁻³ and stabiliser cycles below 50 μs: two to three orders of magnitude faster than neutral-atom implementations.

By extrapolation, the authors estimate that the largest code could reach a logical error probability per qubit per round of 10⁻¹⁴, assuming a ten-fold improvement on early shuttling demonstrations and with other physical errors at p = 0.1%. Gate logic is compatible with NeST too: for the [[150,30,10]] code the authors build a code-surgery gadget in which every qubit moves only by rigid belt motions, at no qubit cost and a 29% increase in gate layers.

The work shows that ultra-low-overhead fault tolerance and a fast clock speed are not competing goals, and that silicon spin qubits can supply both at once. Validating the extrapolations with experimental shuttling demonstrations that achieve the assumed ten-fold improvement remains an open task.